1. Field
Example embodiments relate to a hybrid protection circuit for more efficiently protecting an internal core of a device from both an electrostatic discharge (ESD) event and an electrical over-stress (EOS) event.
2. Description of Related Art
Electrostatic discharge (ESD) is a phenomenon in which a finite quantity of electrostatic charge is rapidly transferred between bodies or surfaces at different electrostatic potentials. The duration of ESD events may range from picoseconds to microseconds. Electrical over-stress (EOS) is an electrical shock caused by a product being exposed to leakage current or voltage (usually from a power supply device or test equipment). The duration of EOS events may range from nanoseconds to milliseconds. As described above, ESD and EOS may have a difference in duration of electrical transient pulse widths.
If an ESD event or an EOS event occurs in a device manufactured by a CMOS process, a thin insulating layer, such as a gate oxide layer, may be damaged. Thus, a circuit for ESD and/or EOS protection may be required. Due to the advances of semiconductor technology, the degree of integration of semiconductor devices has increased and power consumption of semiconductor devices has decreased, and thus, semiconductor devices may be more easily exposed to ESD. When the thickness of a gate oxide layer of a MOS transistor ranges from about 3 nm to about 4 nm, the insulating layer may be damaged and/or destroyed by a voltage ranging from about 3 V to about 4 V. Therefore, a protection circuit protecting the internal core of a device from an ESD event and/or an EOS event may be necessary in this case.
FIG. 1 is a circuit diagram illustrating a conventional gate-grounded NMOS (GGNMOS) transistor. FIG. 2 is a circuit diagram illustrating a conventional gate-coupled NMOS (GCNMOS) transistor.
The GGNMOS transistor having a gate, a source, and a body that are all grounded uses a snap-back phenomenon. As such, the GGNMOS transistor may efficiently protect from an EOS event that has a relatively longer duration of electrical transient pulse widths. However, the GGNMOS transistor may be inefficient in protecting the internal core from an ESD event until the triggering voltage at which the ESD current is discharged through the transistor is reached.
A GCNMOS transistor having a configuration in which the silicide-blocking layer (SBL) has been removed may be employed. The configuration may be efficient to protect the internal core from an ESD event having a relatively shorter duration of electrical transient pulse widths. However, the configuration may be inefficient to protect from an EOS event having a relatively longer duration of electrical transient pulse widths.